1. Field of the Invention
The present invention relates generally to the field of semiconductor devices. More particularly, to the application of carbon nanotube in field effect transistors (FET), and the manufacturing method of producing mass quantity of such transistors at wafer level, while achieving precision positioning of carbon nanotubes as gate channels between source and drain, as well as interconnects.
2. Relevant Background
Carbon nanotube exhibits intriguing electronic properties that give rise to the possibility of being utilized in FETs. As a result of different quantum states depending on the size and chiral structure, nanotubes can behave as semiconductor whose conductivity may be changed by a factor of one million or more, comparable to the change in silicon FET. Because of its tiny size, the nanotube FET has potentially offer significantly lower power consumption, faster switching speed, and better reliability. Metallic nanotubes have the ability to carry a large current density of 109 A/cm2, which is 1000 times higher than the copper wire. This, along with the superior heat conductivity and temperature stability, make the nanotube one of the most attractive interconnect material at extremely miniature feature size.
In prior art, the functionality of a FET device was demonstrated with a nanotube randomly disposed between the source and drain electrodes. This is typically achieved by fabrication of source and drain electrodes using conventional semiconductor manufacturing process (photolithography and patterning), followed by random deposition of nanotubes on the same substrate, and relied on chance that a nanotube with the proper alignment would be found. Another alternative method that has been used in prior art is to deposit nanotubes on a substrate first. This is followed by pattern imaging and recognition using scanning electron microscopy, which was then used to guide the fabrication of contact leads around individual nanotube via e-beam lithography. Both of these techniques are not viable approaches of producing large quantity of nanotube-based devices. Both methods are disadvantageous because of the lack of control over the precise positioning and alignment of nanotubes with respect to the rest of device structure, and the lack of ability to select nanotubes of proper diameter and length.
In prior art, the methods of growing regular array of vertically oriented nanotubes have been shown. One of these methods involves controlled growth of carbon nanotubes on pre-patterned dots of catalysis. Deposition of nanotubes into channels of anodized aluminum has also been used. Both methods are limited to fabrication of vertically aligned nanotubes. They cannot be used to grow in-plane aligned nanotubes, which are required for transistor applications. There are also significant integration challenges between such preparation techniques and conventional semiconductor processing technology.
Therefore, there is a need in the art for a method of fabrication, selection, and integration of such carbon nanotubes into semiconductor electronic devices, such as FET, in particular.